Very Large Scale Integration Design by Dr. Chandra Sekhar Paidimarry M.Tech,Ph.D Gives exposure to different steps involved in the fabrication of ICs using MOS transistor,CMOS/BICMOS transistors and passive components,Gives exposure to the design rules to be followed to draw the layout of any logic circuit,Understand basic programmable logic devices and testing of CMOS circuits Code : VLSIJECE32 Recommended For : B.E/B.Tech 3rd Year(JNTUH,OU)/GATE/Competitive Exams

After Learning this subject,you should be able to

• Acquire qualitative knowledge about the fabrication process of integrated circuit using MOS transistors.
• Design different types of logic gates using CMOS inverter and analyze their transfer characteristics.
• Draw the layout of any logic circuit which helps to understand and estimate parasitic of any logic circuit.
• Design simple memories using MOS transistors and can understand Design of large memories.
• Design simple logic circuit using PLA,PAL,FPGA and CPLD.
• Understand different types of faults thyat can occur in a system and learn the concept of testing and adding extra hardware to improve testability of system.

Curriculum 09:19:54   units   |   8

• 0:47:44

UNIT 1.1
Introduction: Introduction to IC technology Part 1, Introduction to IC technology Part 2, NMOS, CMOS, BiCMOS

• 1:39:27

UNIT 1.2
Basic Electrical Properties: Basic Electrical Properties of MOS and BiCMOS Circuits, Ids-Vds Relationships Part 1, Ids-Vds Relationships Part 2, Ids-Vds Relationships Part 3, gdm,gs, Zp.u/Zp.d, Latch Up, Figure of Merit(w), NMOS Inverter, NMOS VI Characteristics, CMOS inverter analysis and design Part 1, CMOS inverter analysis and design Part 2, CMOS inverter analysis and design Part 3, Power Dissipation of CMOS Inverter, CMOS and NMOS Inverter Delays, MOS transistor acting as Capacitor(1312,13), MOS transistor acting as Resistor(1314,15)

• 0:44:22

UNIT 2
VLSI Circuit Design Processes: Stick Diagrams - Part 01, Stick Diagrams - Part 02, Stick Diagram Example, Design Rules and Layout(1125,1126), Transistor Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of MOS Circuits

• 1:43:40

UNIT 3
Gate Level Design: Logic Gates and Other Complex gates - part 1, Logic Gates and Other Complex gates - part 2, Logic Gates and Other Complex gates - part 3, Pass Transistor part1, Pass Transistor part2, Pass Transistor part3, Propagation Delay-Cascaded Pass Transistor, Dynamic CMOS Design Part 1, Dynamic CMOS Design Part 2, Sheet Resistance and Silicides, Standard unit of capacitance, Problem on Area Capacitance, Delay Unit tow, Driving large capacitive loads, Wiring capacitance, Fan-in,Fan-Out, Choice of Layers

• 1:16:21

UNIT 4
Data path Subsystems: Subsystem Design,,Zero/one detectors, Comparators, Data Path Design, Shifters, Adders - Part 01, Adders - Part 02, Adders - Part 03, Adders - Part 04, Adders - Part 05, Multipliers, Multiplexers, Counters

• 0:47:04

UNIT 4.1
Array Subsystems: Memory Subsystem, ROM, SRAM, DRAM and Serial Access Memories, Bus Arbitration Logic for n-line Bus

• 1:09:16

UNIT 5
Programmable Logic Devices: PLD-Types of PLDs Part 1, PLD-Types of PLDs Part 2, PLAs, PLA Example, FPGAs Part 1, FPGAs Part 2, CPLDs, Standard Cells, Programmable Array Logic, Design Approach

• 1:12:00

UNIT 5.1
CMOS Testing: CMOS Testing & Need for testing- part 1, CMOS Testing & Need for testing- part 2, Design Strategies for test- part 1, Design Strategies for test- part 2, Design Strategies for test- part 3, Design Strategies for test- part 4, Design Strategies for test- part 5, Chip level test techniques, Summary